Regviz

NXP Semiconductors /LPC43xx /USART0 /ICR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ICR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/USART0/ICR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)IRDAEN 0 (NOT_INVERTED)IRDAINV 0 (DISABLED)FIXPULSEEN 0PULSEDIV 0RESERVED

FIXPULSEEN=DISABLED, IRDAINV=NOT_INVERTED, IRDAEN=DISABLED

Description

IrDA control register (USART3 only)

Fields

IRDAEN

IrDA mode enable.

0 (DISABLED): Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART.

1 (ENABLED): Enabled. IrDA mode on USART3 is enabled.
IRDAINV

Serial input direction.

0 (NOT_INVERTED): Not inverted. The serial input is not inverted.

1 (INVERTED): Inverted. The serial input is inverted. This has no effect on the serial output.
FIXPULSEEN

IrDA fixed pulse width mode.

0 (DISABLED): Disabled. IrDA fixed pulse width mode disabled.

1 (ENABLED): Enabled. IrDA fixed pulse width mode enabled.
PULSEDIV

Configures the pulse when FixPulseEn = 1. See Table 885 for details.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data